1. Field of the invention
The present invention relates to a data synchronization circuit and particularly to a data synchronization circuit wherein a phase synchronization is obtained using a clock synchronized with a bit of the relevant received data.
2. Description of the Prior Art
In a digital transmission apparatus, one of the techniques for extracting and reproducing a transmitted digital signal on the receiving side is a bit synchronization technique. In a digital transmission apparatus or the like, it is required to receive a digital signal having a phase variation without errors.
Generally, as one example of bit synchronization circuit used in the transmission of digital signals between a plurality of apparatus operating with a clock supplied from one and the same clock source (synchronized in frequency), "PLL Circuit by Polyphase Clock" described in Japanese Patent Laid-Open No. 43919/1987 is known.
FIG. 14 is a block diagram showing a conventional bit synchronization circuit. In FIG. 14, n-phase clocks 12-1 to 12-n are applied via input clock terminals 2-1 to 2-n to the clock selector 47, which have the same frequency as that of the received data signal and phases different by 360/n (n: integer equal to or greater than 2). This clock selector 47 selects the clock corresponding to a count value of the up-down counter 46 from the n-phase clocks and outputs it to the output clock terminal 9 as an extracted clock 48.
Next, operations will be described. The phase comparison circuit 45 compares the phase of a received data signal 11 inputted via the input data terminal 1 and that of the extracted clock 48. In accordance with the result of phase comparison, the up-down counter 46 performs an increment and decrement in the count value to perform a selective control of the clock selector 47. Thus, by repeating this series of operations, an extracted clock synchronized in phase with the received data signal can be obtained.